Regviz

Espressif Systems /ESP32-H2 /PCR /TIMERGROUP1_CONF

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as TIMERGROUP1_CONF

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Espressif Systems/ESP32-H2/PCR/TIMERGROUP1_CONF#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TG1_CLK_EN)TG1_CLK_EN 0 (TG1_RST_EN)TG1_RST_EN 0 (TG1_WDT_READY)TG1_WDT_READY 0 (TG1_TIMER0_READY)TG1_TIMER0_READY 0 (TG1_TIMER1_READY)TG1_TIMER1_READY

Description

TIMERGROUP1 configuration register

Fields

TG1_CLK_EN

Set 1 to enable timer_group1 apb clock
TG1_RST_EN

Set 0 to reset timer_group1 module
TG1_WDT_READY

Query this field after reset timer_group1 wdt module
TG1_TIMER0_READY

Query this field after reset timer_group1 timer0 module
TG1_TIMER1_READY

reserved

Links

()

Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data